Secure SoC, effective SoC interconnect:
Winners' practices for SoC success
Tuesday, 25.July, Daniel Hotel Herzelia
Hardware-based security solutions offer better protection from manipulation and interference than their software-based counterparts because it’s more difficult to alter or attack the physical device or data entry points. Integrating certified secure solutions such as secure enclaves at the design stage of projects is proving key to SoC vendors, to cover all the upcoming security challenges and cybersecurity requirements for IoT & Mobile applications.
The top-level interconnect of large designs is increasingly challenging. Line delays are long and may become unpredictable, taking at times more than a cycle to complete. Multi-die implementations make it necessary to sustain a network that spans a number of different dies; and complex connectivity protocols must be taken into consideration when setting up the top-level interconnect to successfully deal with all setup / latency / throughput requirements. Thus, not only a NoC creation and management tool but also a complete chip management platform is required, capable to analyze the various players at the SoC’s top level and take a holistic care of the interconnect, while resolving the various requirements that come into play.
Come join us for a half day of high-level interactions and technical discussions, together with a unique representation from our Chip Design Community, in an intimate setting. Tiempo Secure, a world leader in on-chip IP security solutions and security enclaves for strategic embedded security systems, and Signature IP, the providers of the iNoCulator, a configurable and flexible platform for SoC development enabling fast and flexible NoC development, will meet you and present some best practices for the design of your next SoC. You will walk away with some great new ideas on how to improve your SoCs.
This Technology Day is tailored for SoC & System Architects, SoC designers, Design Managers, and SoC Execs. We will enjoy a private venue at the Daniel Herzelia and the company of a selected representation of Israel's SoC Community. All participants will our guests for breakfast and lunch at the Daniel.
Program:
Note: changes to the program or presenters may happen.
8:30-9:00 Registration and breakfast
9:00-9:15 Welcome and agenda
9:15-10:15 Keynote: Shaping the Chiplet Infrastructure Ecosystem: Our Vision and Implementation. by Purna Mohanty, CEO Signature IP
10:15-11:15 Keynote: No Secure Design without Dedicated Hardware - Mikael Dubreucq, VP Global Marketing & Sales Tiempo Secure
11:15-11:45 Networking break; coffee and cakes
13:45-14:00 Wrap-up and raffle
14:00-15:00 Lunch and dispersion
Register to our Technology Day
Our visiting staff:
Purna Mohanty, CEO, Signature IP
Purna brings in 28 years of experience and expertise in engineering, sales, business development, marketing and operations, and connecting these specialties to build a successful business. His love for the Silicon Valley and its technology vibe accompanied by a passion to propagating Silicon Valley's innovative culture around the world drove him to start Marquee and Signature IP with a R&D presence in the "best kept secret" locations around the world. Prior to founding Signature IP and Marquee Semiconductor, Purna held the position of Vice-President Engineering and Operation at Tessolve USA. Purna brings in entrepreneurial vision to his companies. He holds 5 U.S. patents in the area of SoC verification and design. Purna holds a BSEE from NIT Routkela, India, and MSEE from University of Toledo, OH, USA.
Mikael Dubreucq, VP Global Sales and Marketing, Tiempo Secure
Mikael’s own journey to excellence is fueled by his unrelenting drive and passion for emerging technologies and applications. Prior to joining Tiempo’s executive team, Mikaël held several key senior positions in the fields of Marketing, Strategy, Technology Partnerships, Sales, and Business Development. With more than 20 years of experience in sectors including embedded security, digital applications, mobile, connectivity, IoT, secure IPs and semiconductors, Mikaël has worked for recognized multinational companies, including Inside Secure, Valid, HID Global, and Sagem. Mikaël holds a bachelor’s degree in mechanical, electronic & production engineering from the Institute of Technology, France, a master’s degree in international marketing & sales from Skema Business School, France, and an international MBA from Neoma Business School, France.
Sebastien Riou, Sr Application and Innovation Manager, Tiempo Secure
Sebastien, a micro-electronic engineering graduate, with a master’s degree in cognitive science from Grenoble INP – Institute of Technology, he has been working with Tiempo Secure for over 5 years. Prior to this, Sebastien held various engineering roles for key international companies, both in France and abroad. Well-known names include Samsung, NXP, Sony, and NEC, in the sectors of semiconductors, electronics, and smart cards. Sebastien registered several patents related to secure IC implementation, covering aspects of hardware, software, and system architecture. In his present role with Tiempo, Sebastien helps customers to define the security requirements for their products and to plan for the next generation of secure elements that are coming to the market.
Presentations' Abstracts
Keynote: Shaping the Chiplet Infrastructure Ecosystem: The Signature IP Vision and Implementation; by Purna Mohanty
The semiconductor industry is increasingly moving towards small, scalable chiplets for cost-effective, adaptable solutions. Signature IP acknowledges this industry shift and is developing a platform dedicated to the timely and budget-friendly creation of these chiplets. Our flagship IP, the Network-on-Chip (NoC), forms the cornerstone of this initiative, connecting both intra-chip and inter-chiplet transport layers.
This keynote will delve into the rich features of Signature IP's NoC technology and interface solutions. We'll explore how these technologies are being developed and demonstrate how they can be integrated into your silicon designs. We welcome partnerships to collaboratively advance and adopt our technology to propel the silicon design industry forward
Keynote: There is no Secure Design without Dedicated Hardware, by Mikael Dubreucq
There is an increasing number of choices available in embedded security hardware, in response to the growing needs of a very dynamic market. As more and more devices and applications come into circulation, chip manufacturers are focusing their efforts on finding certified secure solutions at the design stage of their projects, to facilitate up-front integration and production. Hardware-based security solutions have already proven to be very successful in providing a higher level of protection against tampering and interference, compared to their software-based counterparts. The robustness of the hardware piece makes it extremely difficult or nearly impossible, to attack or tamper with the physical device or its data entry points. The continued digitalization process for both existing and future applications, such as crypto wallets, digital ID, SIM, etc. will push integrated secure element technology to the forefront, as the next (R)evolution in the field of embedded security for both the IoT and mobile world.
Secure Boot and Secure Enclave in a Post-Quantum World, by Sebastien Riou
Most application-specific integrated circuits (ASIC) include some kind of secure boot. However, due to a lack of standardization within the industry, individual chip manufacturers need to figure out the right architecture for their product, while mobilizing dedicated engineering resources to implement and verify it. Unsurprisingly, the outcome has resulted in many product failures (play station 3, Samsung blue ray players and so many others). This problem is further reinforced by the imminent arrival of quantum computers. This presentation will outline how Tiempo Secure’s TESIC secure enclave protects ASICs from existing threats and future post-quantum threats. A focus will be made on the secure boot of the secure enclave and the application’s central processing unit (CPU).
iNoCulator™ – An Automated Solution for Scalable and Physically-Aware NoC designs., by Purna Mohanty
This presentation includes a live demo. iNoCulator™ is a powerful SaaS-based EDA tool designed to simplify and expedite the process of creating a Network-on-Chip (NoC). With iNoCulator, users can effortlessly explore different NoC topology, configure parameters, and simulate the design to measure essential parameters such as throughput, latency, power requirements, and area.
This innovative tool provides interactive whiteboard editing capabilities, allowing users to connect initiators, routers, and endpoints, simplifying the configuration process. It further supports on-the-fly simulation of bandwidth and latency, along with power and area estimation.
In addition, iNoCulator is equipped with a pushbutton RTL generation feature which directly targets SoC design flows or FPGA emulation flows. This makes iNoCulator a valuable addition to any chip design process, enhancing speed, flexibility, and overall design efficiency.
Common Criteria Certification Made Easy, by Sebastien Riou
Common Criteria certification is the current international ‘gold standard’ for embedded systems security. This certification scheme is the widest available mutual recognition for Secure IP products. It is trusted by governments worldwide for certifying electronic identity and driving licenses, by banks for credit cards, and by mobile network operators for SIM cards. Its applications are continually expanding, and the automotive industry has started using it for access control and for ‘V2X’ communications. Although certification is essential, the process to obtain it is long, complicated, and costly. This can often negatively impact the time-to-market of new products and chip manufacturers don’t always have the time or expertise in-house to meet this challenge. This technical presentation will highlight the benefits of Tiempo Secure’s TESIC secure enclave for optimizing the Common Criteria certification process for ASICs.
PCIe Gen6 Controller IP – A Full-Featured Protocol Layer Supporting Diverse Modes, by Purna Mohanty
PCIe has emerged as the industry standard for host communication due to its robust scalability and speed. Furthermore, its versatility has earned it a prominent place in non-host areas like storage. Signature IP's PCIe Gen6 Controller IP, supporting configurations from x1 to x16 and modes such as Endpoint, Rootpoint, Dual mode (Endpoint or Root), and Switch (Upstream, Downstream), allows you to construct your FPGA and ASIC systems at the highest speed that the SerDes layer can support.
This lecture will delve into the intricacies of the PCIe protocol layer technology developed by Signature IP. We'll discuss how integrating the PCIe controller with the NoC IP can help you create a high-performance system with minimal latency. Join us as we explore the power and potential of our PCIe Gen6 Controller IP in detail.
Register to our Technology Day