Introducing OpenFive's Ethernet Subsystem IP

Designed and tested to be easily synthesizable into many ASIC technologies, the OpenFive Ethernet IP subsystem allows a fast and seamless integration of the IP into your technology of choice.

 

In the sections below, we will go into more details about the OpenFive Ethernet IP Subsystem on all of its components. A comprehensive solution that includes the FlexE IP, the 100G PCS IP core, the 100G MAC IP core and the MCMR Forward Error Correction IP core.  You can get more information on the product briefs of the various cores, HERE.

OpenFive FlexE IP

The OpenFive FlexE IP is fully compliant to the OIF (Optical Internetworking Forum) FlexE v1.0 and v2.0 standard supporting various MAC client rates. Built upon a flexible and robust architecture, OpenFive's FlexE IP supports FlexE aware, FlexE unaware and FlexE terminate modes of mapping over the transport network. 

 

Features: 

The OpenFive FlexE IP core supports various MAC client rates, has a user-configurable client rate adaption, and supports bonding, sub-rate, channelization and hybrid capabilities. It supports up to eight FlexE groups, and re-sizing of FlexE clients within the FlexE group. 

The block diagram above shows the functional representation of how the FlexE relates to the Client and the 100G PCS. A single FlexE can be used to interface up to eight FlexE groups, with each group comprising multiple 100G PCS interfaces.

Designed and tested to be easily synthesizable into many ASIC technologies, the OpenFive FlexE IP is uniquely built to work with off-the-shelf MACs from leading technology vendors, thus allowing for fast and seamless integration of the FlexE IP into your technology of choice.

OpenFive 100G PCS IP Core



Overview:


The OpenFive 100G PCS supports PCS/PMA termination for 100GE, 50GE, 40GE, 25GE and 10GE ports in compliance with 802.3 specifications. 

The Figure below shows a high-level diagram of the 100G PCS IP core. On the system side, a configurable media independent interface provides connection to OpenFive's 100G MAC/RS IP module, to support the 100GE (CGMII), 50GE (50GMII), 40GE (XLGMII, 25GE (25GMII), and 10GE (XGMII) rates.  On the line side, a parallel interface provides direct connection to third-party 4x 25G NRZ and/or 2x 50G PAM4 SERDES modules.  Different bus widths (compile-time) options are provided to support both ASIC and FPGA implementations.

Features:

 

  • Single channel PCS/PMA for 100GE, 50GE, 40GE, 25GE and 10GE Ethernet ports.

  • Compile-time bus width options to support ASIC and FPGA implementations.

  • Compile-time and run-time configuration options to support PCS and PMA termination for Ethernet PHYs based on the 66b encoding (clauses 82/133/107/49), the BASE-R / Fire Code FEC (clause 74), the KR FEC (clauses 91/108), the KP FEC (clauses 91/134), and the Consortium LL-FEC.

  • Media independent interface:

    • A flexible CGMII/XGMII port, providing seamless connection to OSi's 100G MAC/RS IP module.

    • Supports CGMII/XLGMII (clause 81), 50GMII (clause 132), 25GMII (clause 106) and XGMII (clause 46) operation modes.

  • SerDes interface

    • SerDes parallel interface options for 25G NRZ lanes, 50G PAM4 lanes, and future 100G PAM4 lanes.

  • BASE-R processing

    • 66b block lock, AM lock/deskew/reorder, AM insertion/deletion and scrambling for Ethernet ports based on the 66b and Fire Code FEC encodings.

    • Per-lane programmable markers.

    • Automatic consequent actions.

    • Scrambled Idle Test pattern, Hi BER detection.

    • Lock alarms, HiBER alarm, BIP statistics.

  • Fire Code FEC

    • Compliant with 802.3 clause 74, for the support of 100GE, 40GE, 25GE, 10GE cable and backplane PHYs.

    • Optional 66b block error marking.

    • Corrected and uncorrected block counters.

  • Reed Solomon FEC

    • Compliant with 802.3 clauses 91, 134 and 108, for the support of 100GE/50GE/25GE optical, cable and backplane PHYs.

      • RS10 (544, 514, t=15) KP FEC.

      • RS10 (528, 514, t=7) KR FEC

    • Compliant with the Consortium low latency FEC (LL-FEC) for 25GE.

      • RS10 (272, 257+1, t=7) 

    • Transcoding, scrambling and alignment marker insertion/deletion (programmable markers).

    • AM lock / deskew / reorder of four 25G FEC lanes (100GE) or two 25G FEC lanes (50GE).

    • Symbol distribution.

    • FEC degrade functionality for 100GE and 50GE.

    • Optional error indication functionality (for 66b sync header corruption), and optional error monitoring (>K errors every 8k codewords).

    • Alarms and monitoring counters (e.g. symbol errors, corrected /uncorrected codewords, etc).

  • PMA

    • Compliant with 802.3 clauses 83, 135, 109 and 51.

    • Test pattern generation for NRZ's PRBS31, PRBS9 and square-wave, and PAM4's PRBS31Q, PRBS13Q and SSPRQ.

    • Remote and local loopbacks.

  

OpenFive 100G MAC IP Core


Overview:

 

The OpenFive 100G MAC IP core supports MAC/RS termination for 100GE, 50GE, 40GE, 25GE, 10GE, 5GE, 2.5GE and 1GE incompliance with 802.3 specifications. The figure below shows a high-level diagram of the 100G MAC IP core.

On the system side, the user interface provides connection to the customer-side packet buffers. The user I/F provides sideband signals for packet delineation, packet error, link status, and Ethernet flow control indications. Customer-specific request-response delays are tolerated using a FIFO.

On the line side, three separate xMII interfaces are provided for connection to specific PCS/PMA modules: a flexible CGMII/XGMII port, for connection to OSi's 100G PCS/PMA companion module, an XGMII port, for connection to a third-party 25/10/5/2.5GE PCS/PMA module, and a GMII port, for connection to a third-party 1GE PCS/PMA module.

Compile-time bus width options are provided to support both ASIC and FPGA implementations.
 

The 100G MAC terminates the MAC and RS sublayers, inserting/deleting the Preamble/SFD, FCS and IPG fields, generating/terminating the control characters used to delineate the packets and encode explicit fault indications, and adapting the packet stream to/from the active media independent interface.

The 100G MAC supports both classic (802.1x) and class-based (802.1Qbb) Ethernet flow control. Pause frames are generated, using the configured Pause quanta values. The received Pause frames are detected by correctly matching the DA, EtherType and Opcode fields.


Features:
  • Single channel MAC/RS for 100GE, 50GE, 40GE, 25GE, 10GE, 5GE, 2.5GE and 1GE MAC ports.

  • Compile-time bus width options to support both ASIC and FPGA implementations.

  • Optional classic (802.3x) and priority-based flow control (802.1Qbb).

  • MAC layer processing, including full statistics (IEEE 802.3, IETF RFC 2665 MIB/MIB-II and RFC 2819 RMON counters), in both transmit and receive directions.

  • Supports VLAN tagged frames (IEEE 802.1Q) and double-tagged frames (QinQ).

  • OAM, LACP, BPDU frame detection.

  • Non-pause control frames optionally dropped.

  • All frames are subject to configurable minimum and maximum frame length checks.

  • Preamble/SFD and FCS are deleted/inserted or bypassed to/from the user interface.

  • Option to overwrite SA on transmitted frames.

  • Option to drop received frames that do not match configured DA.

  • Option to filter packets that do not match.

  • FCS checking and generation.

  • Supports padding of small (<64 byte) frames.

  • Interpacket gap generation based on Deficit Idle Counter (100/50/25/10/5G/2.5GE) or using a fixed length (1GE).

  • Link status automatic consequent actions (LF−›RF, RF−›Idle reflections).

  • Compliant with 802.3 clause 78 (802.3az standard) for Energy Efficient Ethernet (EEE).


User Interface:
  • Simple user (MAC service) interface, consists of a single segment of 128, 256, 512 or 1024 bits.

  • Input/output sideband signals to control/ indicate packet delineation, packet errors, Ethernet link status, and Ethernet flow control.

  • Tolerates arbitrary request-response delays on the transmit direction.


Media independent interface:

Three separate media independent interfaces provide connection to specific PCS/PMA modules:

  • A CGMII/XGMII port, for connection to OpenFive’s 100GE, 50GE, 40GE, 25GE and 10GE PCS/PMA module, to implement PHYs based on 66b (clauses 82/133/107/49), KR FEC (clauses 91/108), KP FEC (clauses 91/134), and Fire Code FEC (clause 74).

  • An XGMII port, for connection to a third-party 25/10G/5/2.5GE PCS/PMA module (e.g. 25GBASE-T).

  • An GMII for connection to a third-party 1GE PCS/PMA module (e.g. 1000BASE-T).


Ethernet flow control:
  • Supports both classic (802.3x) and class based (802.1Qbb) Ethernet flow control.

  • Pause frame generation is controlled through the user I/F Xon/Xoff input sideband signals.

  • Pause frames generated using programmable pause quanta values and retransmitted using a configurable retransmission interval.

  • Received Pause frames detected by correctly matching the DA, EtherType and Opcode fields.

  • Extracted pause quanta values are loaded into decremented counters that control the Xon/Xoff indications sent to the user I/F.


Precision timing:
  • IEEE 1588v2 support using an optional module.

  • Implements Transparent Clock, and assists external software in the support of Master, Slave and Boundary Clock functionality, for the Ethernet, IPv4 and IPv6 encapsulations, in either one-step or two-step mode.

  • Assists external software to support other encapsulations no defined by IEEE 1588-2008, such as MPLS or MAC-in-MAC.

 

 

OpenFive MCMR FEC (Forward Error Correction) IP Core

Multi-Channel Multi-Rate FEC IP:

OpenFive’s MCMR FEC IP core is a single solution to meet the requirements of different protocols like Interlaken, Flex Ethernet, and 802.3x to significantly improve bandwidth by enabling high speed SerDes integration. The FEC can easily achieve a BER (Bit Error Rate) of 10-6 , which is required by most electrical interface standards using high speed SerDes.

Built upon a flexible and robust architecture, OpenFive’s MCMR FEC IP core is compatible with various SerDes supporting different widths. The MCMR FEC IP supports bandwidth up to 400G with the ability to connect 32 SerDes lanes.


Features:
  • Supports up to 56Gbps SerDes

  • Supports bandwidth up to 400G

  • Support for KP4 RS (544,514) & KR4 RS (528,514)

  • Supports Interlaken, Flex Ethernet & 802.3x protocols

  • Supports configurable alignment marker

  • PRBS test pattern generator and loopback test


The block diagram below shows the functional representation of how the FEC relates to the protocol layer and the SerDes lanes. As an example, a single MCMR FEC can be used to interface with up to 32 SerDes lanes with an aggregate bandwidth of up to 400G. Likewise, to achieve a 1.2Tbps bandwidth with 24 lanes 50G SerDes interface, you would need three instances of MCMR FEC IP.
 

Deliverables:

OpenFive’s Ethernet IP cores are shipped with the following deliverables:

  • Synthesizable RTL

  • Template CAD scripts for synthesis and static timing

  • Assertions for the user interface and config registers

  • Sanity test simulation environment

  • RX/TX BFMs

  • Documentation:

    • OpenFive IP Specification

    • Memory-Mapped Register Manual

    • Design Verification Plan

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