Introducing OpenFive's HBM2/2E Memory Subsystem IP

Today's advanced FinFET designs are often 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what's been called the "more than Moore" revolution associated with 2.5 and 3D design, you know that HBM memory stacks essentially paved the way for this revolution.  The HBM memory specification is alive and well with new, high-performance versions available today - and more in the pipeline.

What is HBM and why do you need it?  HBM memory stacks are actually very dense memory subsystems implemented with 3D packaging technology. The latest implemented version of the specification is HBM2E. OpenFive prepared a useful table below that summarizes what the latest HBM2E spec can deliver when compared with more traditional memory technologies. Take a good look at the density, power efficiency and bandwidth lines:


If your application needs ultra-dense, high-performance memory, HBM is really the only practical path forward. OpenFive offers an HBM2/HBM2E IP subsystem that provides the critical elements of an Integrated HBM controller and HBM PHY that support both the HBM2 and HBM2E standards in multiple fab technologies. Below is a summary of the substantial technology and support offered by OpenFive and their HBM2/2E subsystem. Note that CoWoS stands for chip-on-wafer-on-substrate, a 2.5D technology offered by TSMC.

  • One Stop Solution: PHY and Controller - Yes.

  • 2.5 Interposer Design Service - Yes

  • Full ASIC Design Service - Yes

  • >7 Years 2.5D Based IP Experience - Yes

  • CoWoS Experience - Yes


In the section below, we will go into more details on the OpenFive HBM2/2E IP Subsystem, a comprehensive solution for HBM2/2E Controller, PHY and I/O, pre-integrated and pre-verified.  It is also worth noting that our HBM3 solution is on the works - stay tuned!


HBM2/2E High Bandwidth Memory

Comprehensive HBM2/2E Controller, PHY and I/O Solution


The OpenFive HBM2/E IP subsystem solution is architected and designed to provide the highest performance and flexibility

for integrating high-bandwidth memory directly into next-generation ASIC and SoC SiP solutions.




OpenFive's HBM2/2E IP is the industry's first comprehensive solution for integrating high-bandwidth memory into ASICs, thereby achieving the ultimate high performance and low power. By integrating the HBM2/2E protocol controller, PHY and I/O into one subsystem IP product, interoperability issues between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies, and by leveraging its experience from the industry's first successful 2.5D SoC SiP demonstration, OpenFive plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.


The OpenFive HBM2/2E IP fully complies with the HBM2/2E JEDEC(c) standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. Besides the controller, the IP includes the PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer.

Subsystem schematic representation:

IP Deliverables:

  • Synthesizable RTL

  • Example EDA scripts

  • Test bench

  • Assertions for user interface and configuration registers

  • PHY and I/O delivery as single hardened IP:

    • GDSII (micro bump included)

    • LVS netlist

    • Verilog models for simulations

    • LIB timing model

    • LEF (micro bump included)

  • Documentation

    • IP specifications

    • Design verification plan.



OpenFive's HBM2 IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP platform. The platform is used to demonstrate the high bandwidth data transfer and interoperability between OpenFive's HBM2 IP subsystem and HBM2 memory die-stack.


The platform provides up to 256 GB/s at 1.6-2Gbps data transfer rates. The interposer trace langths are up to 5mm. Built in TSMC 16nm, using the TSMC 65nm interposer and the TSMC CoWoS (2.5D) SiP. The design features  HBM2 memory and OpenFive's HBM2 IP Subsystem (Controller + PHY + I/O) in a 27mm x 27mm package. The interposer size is 14.75mm x 11.65mm, core voltage is 0.8V and I/O voltage is 1.2V.


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