Introducing OpenFive's Interlaken Subsystem IP

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Interlaken Subsystem IP Core

Chip2Chip Interface

The eighth generation of OpenFive Interlaken IP core improves the bandwidth to over 1.2Tb/s while at the same time reducing the area and power. Building upon the flexible and robust architecture, the OpenFive Interlaken IP core has "pipe efficiency" and "67-bit SerDes slice", which saves significant area while at the same time allows the IP to run at a lower frequency thus saving power. The "pipe efficiency" feature saves significant area by reducing the number of pipes (64b internal datapaths) by efficiently mapping the pipes to SerDes lanes while reducing the required clock frequency. The "67b SerDes slice" feature allows the IP to operate the SerDes slice functionality in a single clock cycle (2 cycles previously) thus reducing required clock frequency.

 

Key Features

  • Fully-programmable SerDes lane mapping

  • Interlaken-LA 4-channel protocol

  • Up to 56 Gbps SerDes support

  • 1.2Tbps high-bandwidth performance

  • Interlaken Retransmit Extension support

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Multiple Aggregate Bandwidth Interfaces

The block diagram above shows a functional representation of the multiple aggregate BW interfaces. As an example, a single Interlaken IP instance can be configured in-system to support different Interlaken interfaces: 1x1.2Tbps, 2x600Gbps or 4x300Gbps, leading to a more area efficient and flexible implementation.

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Standard Features:

In addition to the key features highlighted above, the OpenFive Interlaken IP Subsystem also provides the following feature set as part of the standard IP functionality:
 

  • Support for 256 logic channels

  • 8-bit channel extension for up to 64K channels

  • Independent SerDes lane enable/disable

  • Support for SerDes speeds from 3.125 Gbps to 56 Gbps

  • Configurable number of lanes - from 1 to 48

  • Flexible user interface options:

    • 128b: 1x128b, 2x128b, 4x128b, or 8x128b

    • 256b: 1x256b, 2x256b, 4x256b, or 8x256b

  • Programmable BURSTMAX from 64 to 512 bytes

  • Programmable BURSTMIN from 32 to 256 bytes

  • Simultaneous In-band and Out-of-Band flow control

  • Programmable calendar

  • Build-in error detection and interrupt structures

  • Configurable error injection mechanisms for testability

  • Full-packet mode and segment mode

  • SerDes support for 8,10,16, 20, 32, 40, 64, 80 bits

  • Maintenance interface for control and configuration

  • Flexible statistics counters

  • Debug Features: PRBS generators / checkers and loopback support for both data and flow control.

Interlaken Low-Latency (ILKN-LL) IP Core


Extending on the 8th generation of its Interlaken Subsystem IP Core, OpenFive now introduces a Low-Latency version of the Chip2Chip and Die2Die connectivity Interlaken IP, used across many applications. Cutting edge technologies such as High Performance Computing (HPC) clusters, AI/ML chip clusters, IoT edge devices, networking and switching fabrics, re demanding high throughput data transfers from one chip to another at a very low latency. Interlaken-LL includes a validation platform supporting up to 256 Gbps.

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Key Features

  • User Interface options:

    • 1x64-bit

    • 2x64-bit

    • 4x64-bit

  • Support for up to 8 lanes

  • Support for up to 4 internal pipes

  • Retransmit Feature in two modes:

    • Cut-through mode [RX side] - Default

    • Store-and-Forward mode [RX side] - Selectable

  • Reduction of overall data path latency

  • Support for NRZ SerDes up to 32 Gbps

  • Configurable Asynchronous FIFO - Optional

  • Configurable SerDes width up to 64-bit

  • Simultaneous In-band and Out-of-Band flow control

 

Standard Features

  • Support for 256 logic channels

  • 8-bit channel extension for up to 64K channels

  • Independent SerDes lane enable / disable

  • Programmable BURSTMAX from 64 to 512 bytes

  • Programmable BURSTMIN from 8 to 128 bytes

  • Simultaneous In-band and Out-of-Band flow control

  • Programmable calendar

  • Build-in error detection and interrupt structures

  • Configurable error injection mechanisms for testability

  • Support for internal and external loopback modes and SerDes testability using test pattern

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