The Future of RISC-V has no limits

Explore the Network on Chip and Interconnect Architecture with best performance and max flexibility

 

Signature IP’s mission is to enable our customers to rapidly and efficiently explore the Network On Chip (NoC) and interconnect architectures for their SoCs and achieve the best possible performance. We aim to speed our customers to market via top-down design exploration and optimization, configurability and flexibility, and excellent customer support.

 

The company was started in 2021 in Sunnyvale, California, as a spin-off of Marquee Semiconductor Inc. and focuses on tool-based platform solutions around NoC, PCIe and CXL.

 

The iNoCulator™ is a SaaS-based EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to measure throughput and latency, power requirements and area. iNoCulatorTM enables interactive whiteboard editing of the NoC topology, through connection of initiators, routers and endpoints, and easy configuration. It supports on-the-fly instant simulation of bandwidth and latency, and estimation of power and area. iNoCulatorTM provides pushbutton RTL generation with targets to an SoC design flow or to an FPGA emulation flow.

 

With Signature IP, the iNoCulator tool can be used as the chip design platform for incrementally building up and refining the timing of your chip. You start with initial representations of your main blocks, and incrementally replace them by more advanced representations (outline => post rtl => gate level, etc.), while exploring the resulting timing and increasingly improving the NoC architecture to meet your performance goals.

 

C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It has configurable data bus widths, supports multiple clocking schemes, and is physically aware with auto-pipelining and grouping of routers to meet timing requirements. C-NoC supports multiple protocols including CHI, AXI4/3 and AXI-lite, ACE and ACE-lite.

 

NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC supports multiple clocking schemes and multiple protocols such as AXI4/3, AHB, APB, AXI-lite and multiple bus widths from 32 to 2048 bits. It provides power control through power-islanding and a power-gating architecture at the interface port and router level. NC-NoC is physically aware, providing automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and generation of power and frequency-aware NoC generation.

 

NC-NoC delivers high performance though any-to-any connections at multiple levels. Its packetized architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.

 

A unique feature of the Signature IP NoCs is their understanding of various connectivity protocols and the ability to sustain the NoC through these protocols. Thus, for example, a multi-die SoC designer will be able to see a single NoC that crosses the boundaries of the individual dies and encompasses the whole multi-die chip.

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Your NoC as the chip design platform for incrementally building up and refining the timing of your chip

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