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Welcome to IPro Silicon IP Ltd.
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About IPro:

IPro licenses Silicon IP to the Israeli Chip Design Community, from selected IP companies world-wide. We deliver key functionality for your design through best-in-class IP partnerships and first-class support. 

We act as one company. Operating at the same high standards of support and commitment that you have learned to trust along years of partnership with me in a variety of Sales roles, the IPro Group continues a long tradition of engaged support and information exchange. We inform you, learn your needs, and provide IP solutions for your SoC design challenges, enabling you to reach the market with world-class IP products - fast!

Imagine a vibrant community of Israeli fabless companies and Worldwide IP vendors, collaborating closely and sharing information. Imagine an atmosphere of trust and cooperation and mutual commitment - for the success of your designs and for the constant improvement of our IP offer. This is the IPro vision - a one-stop shop of state-of-the-art IP with unique engagement and bond with our Partners. 

About our IP Vendor Partners:


The Future of RISC-V has no limits

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute and defining what comes next.

The RISC-V revolution didn’t just push boundaries - it removed them entirely. At SiFive, we’ve harnessed its limitless potential and empowered all companies to deliver the most advanced solutions of tomorrow.

We are not preparing for the future - we are making it happen! If you believe in RISC-V, you need SiFive. Whether you want to shape the next era of application-specific hardware, or build a career collaborating with the most talented leaders in technology, SiFive enables you to innovate for tomorrow, today.

300+ design wins with over 100 companies including 8 of the top 10 semiconductor companies

We enable the shift to a high performance future with a portfolio of powerful and efficient RISC-V cores. Our software-first approach unlocks the potential you need to take ownership of tomorrow.

  • The highest performing compute platform in the RISC-V architecture

  • A complete portfolio of powerful, configurable RISC-V processors

  • An undeniable industry lead in velocity, scalability and talent

Join the leaders of the RISC-V Revolution in your next design!

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Certified Security for IC Design

Tiempo Secure is a unique security provider for semiconductor designers, based in Montbonnot Saint-Martin, France. For over 13 years, Tiempo has developed security IP, secured software libraries and security expertise to allow their customers to reach the highest and certified levels of security for their SoCs and products.


The flagship IP of Tiempo Secure is the TESIC RISC-V, a Common Criteria EAL5+ PP0117-ready Security Enclave IP. It includes a 32-bit RISC-V microprocessor, secure cryptographic processors and hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test. TESIC is guaranteed to pass CC EAL5+ PP0117 and / or EMVCo security certification of the chip integrating this macro.


A unique service provided by Tiempo Secure is to manage the entire CC EAL5+ PP0117 (or similar) security certification of customer chips integrating the TESIC certification-ready cores. The work includes the writing of the CC-compliant documentation, the preparation of the customer chip samples and boards for the validation, the support of the ITSEF labs during customer chip evaluation and certification, and the interactions with the national cybersecurity agency to obtain the CC certification.


Other great value Products and Services are also available - you can find them in the Tiempo Secure web.

TESIC secure element IP cores and secure SW libraries guaranteed for CC EAL5+ certification

Security services include custom secure design, chip CC certification and setup of CC/GSMA compliant HSM servers


Explore the Network on Chip and Interconnect Architecture with best performance and max flexibility


Signature IP’s mission is to enable our customers to rapidly and efficiently explore the Network On Chip (NoC) and interconnect architectures for their SoCs and achieve the best possible performance. We aim to speed our customers to market via top-down design exploration and optimization, configurability and flexibility, and excellent customer support.


The company was started in 2021 in Sunnyvale, California, as a spin-off of Marquee Semiconductor Inc. and focuses on tool-based platform solutions around NoC, PCIe and CXL.


The iNoCulator™ is a SaaS-based EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to measure throughput and latency, power requirements and area. iNoCulatorTM enables interactive whiteboard editing of the NoC topology, through connection of initiators, routers and endpoints, and easy configuration. It supports on-the-fly instant simulation of bandwidth and latency, and estimation of power and area. iNoCulatorTM provides pushbutton RTL generation with targets to an SoC design flow or to an FPGA emulation flow.


With Signature IP, the iNoCulator tool can be used as the chip design platform for incrementally building up and refining the timing of your chip. You start with initial representations of your main blocks, and incrementally replace them by more advanced representations (outline => post rtl => gate level, etc.), while exploring the resulting timing and increasingly improving the NoC architecture to meet your performance goals.


C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It has configurable data bus widths, supports multiple clocking schemes, and is physically aware with auto-pipelining and grouping of routers to meet timing requirements. C-NoC supports multiple protocols including CHI, AXI4/3 and AXI-lite, ACE and ACE-lite.


NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC supports multiple clocking schemes and multiple protocols such as AXI4/3, AHB, APB, AXI-lite and multiple bus widths from 32 to 2048 bits. It provides power control through power-islanding and a power-gating architecture at the interface port and router level. NC-NoC is physically aware, providing automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and generation of power and frequency-aware NoC generation.


NC-NoC delivers high performance though any-to-any connections at multiple levels. Its packetized architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.


A unique feature of the Signature IP NoCs is their understanding of various connectivity protocols and the ability to sustain the NoC through these protocols. Thus, for example, a multi-die SoC designer will be able to see a single NoC that crosses the boundaries of the individual dies and encompasses the whole multi-die chip.

Your NoC as the chip design platform for incrementally building up and refining the timing of your chip

About myself (M.Diamant):


I am the General Manager of IPro.  Prior to IPro, I executed multiple sales and engineering management functions in the IP business for more than 30 years, in a variety of companies such as DEC, Zoran, LSI, Avant!, MIPS and ARM. At IPro, I have represented a wide variety of IP disciplines including Processors, Connectivity, Advanced Memory Systems, NoC, Security, Machine Learning and Automotive Platforms.  I have a EE B.Sc. and a Marketing MBA, both from the Technion in Haifa. I am Israeli by choice and have been living in this great country for more than 40 years. LinkedIn Profile.

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Events & Occasions

Tiempo Secure & Signature IP Technology Day: 

Secure SoC, effective SoC interconnect: Winners' practices for SoC success

Tuesday, 25.July, Daniel Hotel Herzelia

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Some of the Topics to be discussed:

  • The SoC and Chiplet Infrastructure Ecosystem:

    • Signature IP's vision for Fast SoC Closure.

    • A NoC Platform dedicated to timely and budget-friendly creation of Chiplets.

    • How can the iNoCulator IP help me manage this activity?

    • Live demo: NoC creation, topology exploration, on-the-fly simulation, RTL generation.

    • The business case for a NoC SaaS model.


  • PCIe Gen6 Controller for the masses:

    • Same IP for FPGA, SoC or Chiplet?

    • What if I need Gen5? Or even Gen4??? 

    • The benefits of a NoC-aware PCIe interface.

  • How to boot a REALLY Secure SoC?

    • Tiempo Secure's vision for a Secure Connected World

    • There is no security without a perfect combination of Hardware and Software.

    • What is the value of a Secure Enclave?

    • About Threat Surface and Secure Boot.

    • Post Quantum challenges.

  • What does it take to obtain Common Criteria Certification?

    • Good standards of Security Certification.

    • A Long, Complicated and Costly Road...

    • Advantages of TESIC to Optimize the Certification Process.

    • What expertise and assistance can Tiempo Secure provide me with?

Participation is free but requires early registration. Please register now!

The RISC-V Summit Europe: June 5-9, Barcelona

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Articles, Papers
Feature Highlight: Tiempo Secure's TESIC RISC-V CC EAL5+ Secure Enclave
Feature Highlight: Signature-IP's iNoCulator TM  NoC Builder and SoC Design Platform
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